2005 Guru Gobind Singh Indraprastha University B C A Computer Application Digital Electronics Question paper for exam preparation. Question paper for 2005 Guru Gobind Singh Indraprastha University B C A Computer Application Digital Electronics Question paper, 2005 Guru Gobind Singh Indraprastha University B C A Computer Application Digital Electronics Question paper. SiteMap

## Exam Preparation

 • AIPMT Exam Preparation • Civil Services Exam Preparation • IIT JEE Exam Preparation • Class 12th Standard Exam Preparation • Class 11th Standard Exam Preparation • Class 10th Standard Exam Preparation • Class 9th Standard Exam Preparation • Class 8th Standard Exam Preparation

## Question Papers

 • Class 9th Standard Question Paper • Class 10th Standard Question Paper • Class 11th Standard Question Paper • Class 12th Standard Question Paper • BA Question Paper • BBM Question Paper • BCA Question Paper • BCom Question Paper • BE Question Paper • BSc Question Paper • BTech Question Paper • LLB Question Paper • LLM Question Paper • MA Question Paper • MBA Question Paper • MCA Question Paper • MCom Question Paper • MSc Question Paper • MTech Question Paper

# 2005 Guru Gobind Singh Indraprastha University B C A Computer Application Digital Electronics Question paper

University Question Papers
2005 Guru Gobind Singh Indraprastha University B C A Computer Application Digital Electronics Question paper
END-TERM EXAMINATION
SECOND SEMESTER [BCA] - MAY 2005
Paper Code: BCA106 Subject: Digital Electronics

Time : 3 Hours Maximum Marks : 75

Note: Attempt any five questions.

Q.1 (a) Simplify the following four variable equation. (8)
K = f(A, B, C) = p (1, 2, 3, 9, 12, 14)
(b) Find the DeMorgan equivalent to following equations: (7)
F = XYZ + XZ + X’Y’ + YZ

Q.2 (a) Design a full subtractor using 3.8 decoder and OR Gates. (8)

Q.3 (a) Design Binary-to-Gray code converter. (8)
(b) Design a Binary multiplier Circuit. (7)

Q.4 (a) Design a J-K flip-flop using NAND gate and explain it. (8)
(b) Explain Race-Around condition. Discuss the technique to
avoid race around condition. (7)

Q.5 (a) Explain parallel- in-serial out shift Resister in detail. (8)
(b) Explain Bi-directional shift Register. (7)

Q.6 (a) Design a Decode Counter. (8)
(b) Des ign a 4-Bit up-down Counter. (7)

Q.7 Write a short notes (any three): - (15)
(a) RTL
(b) TTL
(c) DTL
(d) CMOS Logic